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1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M51008BP,FP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for the battery back-up application. The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).Two types of devices are available. VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
PIN CONFIGURATION (TOP VIEW)
NC 1 A16 2 A14 3 A12 4 5 A7 6 A6 7 A5 8 A4 9 A3 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 GND 16
32 31 30 29 28
27 26 25 24 23 22 21 20 19 18 17
ADDRESS INPUTS
FEATURES
Power supply current
Type name
M5M51008BP,FP,VP,RV,KV,KR-55L M5M51008BP,FP,VP,RV,KV,KR-70L M5M51008BP,FP,VP,RV,KV,KR-10L M5M51008BP,FP,VP,RV,KV,KR-55LL M5M51008BP,FP,VP,RV,KV,KR-70LL M5M51008BP,FP,VP,RV,KV,KR-10LL
Access time (max)
Active (1MHz) (max)
stand-by (max)
DATA INPUTS/ OUTPUTS
55ns 70ns 100ns 55ns 70ns 100ns
VCC ADDRESS A15 INPUT S2 CHIP SELECT INPUT W WRITE CONTROL INPUT A13 A8 ADDRESS INPUTS A9 A11 OE OUTPUT ENABLE INPUT A10 ADDRESS INPUT S1 CHIP SELECT INPUT DQ8 DQ7 DQ6 DATA INPUTS/ DQ5 OUTPUTS DQ4
M5M51008BP,FP-I
15mA
200A
(Vcc=5.5V)
Outline 32P4(P), 32P2M-A(FP)
A11 A9 A8 A13 W S2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26
40A
15mA
(Vcc=5.5V)
0.3A
(Vcc=3.0V,typ)
Single +5V power supply Low stand-by current 0.3A (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by S1,S2 Data hold on +2V power supply Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51008BP ************ 32pin 600mil DIP M5M51008BFP ************ 32pin 525mil SOP M5M51008BVP,RV ************ 32pin 8 X 20 mm 2 TSOP M5M51008BKV,KR ************ 32pin 8 X 13.4 mm 2 TSOP
OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3
M5M51008BVP,KV-I
25 24 23 22 21 20 19 18 17
APPLICATION
Small capacity memory units A4 A5 A6 A7 A12 A14 A16 NC VCC A15 S2 W A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Outline 32P3H-E(VP), 32P3K-B(KV)
17 18 19 20 21 22 23
M5M51008BRV,KR-I
24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE
Outline 32P3H-F(RV), 32P3K-C(KR)
NC : NO CONNECTION
1
MITSUBISHI ELECTRIC
1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008B series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1 X H L L L S2 L X H H H W X X L H H Mode DQ OE X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H ICC Stand-by Stand-by Active Active Active
BLOCK DIAGRAM
* A4 A5 A6 A7 8 7 6 5 16 15 * 21 13 DQ1 14 DQ2 15 DQ3 17 DQ4 18 DQ5 19 DQ6 20 DQ7 21 DQ8 DATA INPUTS/ OUTPUTS 22
ADDRESS INPUT BUFFER
13 12 11 10 7 4 3
OUTPUT BUFFER
14
ROW DECODER
A12 4 A14 3 A16 2 A15 31 A13 28 A8 27
131072 WORDS X 8 BITS (1024 ROWS X128 COLUMNS X 8BLOCKS)
SENSE AMP.
23 25 26 27 28 29
ADDRESS INPUT BUFFER
A2 10 A3 9
18 17 31
A10 23
COLUMN DECODER
A0 12
20
CLOCK GENERATOR
DATA INPUT BUFFER
ADDRESS INPUTS
5 ADDRESS INPUT BUFFER
WRITE 29 W CONTROL INPUT 22 S1 30 S2 CHIP SELECT INPUTS
BLOCK DECODER
A1 11 A11 25 A9 26
19 1 2
30 6 32 8 24
OUTPUT 24 OE ENABLE INPUT 32 VCC GND 16 (0V)
* Pin numbers inside dotted line show those of TSOP
2
MITSUBISHI ELECTRIC
1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings - 0.3*~7 - 0.3*~Vcc + 0.3 0~Vcc 700 - 40~85 - 65~150 Unit V V V mW C C
* -3.0V in case of AC ( Pulse width 30ns )
DC ELECTRICAL CHARACTERISTICS (Ta = -40~85C, Vcc=5V10%, unless otherwise noted)
Symbol VIH VIL VOH1 VOH2 VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage 1 High-level output voltage 2 Low-level output voltage Input current Output current in off-state Active supply current (AC, MOS level) Test conditions Min 2.2
-0.3*
Limits Typ Max
Vcc +0.3V
Unit V V V V 0.4 1 1 V A A
0.8
IOH= -0.5mA IOH= -0.05mA IOL=2mA VI=0~Vcc S1=VIH or S2=VIL or OE=VIH VI/O=0~VCC S10.2V,S2Vcc-0.2V, other inputs0.2V or Vcc-0.2V Output-open(duty 100%) S1=VIL,S2=VIH, other inputs=VIH or VIL Output-open(duty 100%) 1) S2 0.2V 2) S1 VCC-0.2V, S2 VCC-0.2V other inputs=0~VCC S1=VIH or S2=VIL, other inputs=0~VCC Min cycle 1MHz Min cycle 1MHz -L -LL
2.4
Vcc -0.5V
ICC1
35 (40)** 4 38 (43)** 5
70 (80)** 15 70 (85)** 15 100
mA
ICC2
Active supply current (AC, TTL level)
mA
ICC3
Stand-by current
A 20 3 mA
ICC4
Stand-by current
* -3.0V in case of AC ( Pulse width 30ns ) ** inside ( ) is a value of -55L,-55LL
CAPACITANCE (Ta = -40~85C, Vcc=5V10%, unless otherwise noted)
Symbol CI CO Parameter Input capacitance Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ Max 6 8 Unit pF pF
Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 5V, Ta = 25C
3
MITSUBISHI ELECTRIC
1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = -40~85C, Vcc=5V10%, unless otherwise noted) (1) MEASUREMENT CONDITIONS
Input pulse level ************** VIH=2.4V,VIL=0.6V (-70L,-10L,-70LL,-10LL) VIH=3.0V,VIL=0.0V (-55L,-55LL) Input rise and fall time ***** 5ns Reference level **************** VOH=VOL=1.5V Output loads ********************* Fig.1,CL=100pF (-10L,-10LL,) CL=30pF (-55L,-70L,-55LL,-70LL) CL=5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
VCC
1.8k DQ 990 CL ( Including scope and JIG )
Fig.1 Output load
(2) READ CYCLE
Symbol tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address -55L,LL Min Max 55 55 55 55 30 20 20 20 5 5 5 5 Limits -70L,LL Min Max 70 70 70 70 35 25 25 25 10 10 5 10 -10L,LL Min Max 100 100 100 100 50 35 35 35 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
(3) WRITE CYCLE
Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low -55L,LL Min Max 55 45 0 50 50 50 25 0 0 20 20 5 5 Limits -70L,LL Min Max 70 55 0 65 65 65 30 0 0 25 25 5 5 -10L,LL Min Max 100 75 0 85 85 85 40 0 0 35 35 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
4
MITSUBISHI ELECTRIC
1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS Read cycle
tCR A0~16 ta(A) tv (A)
ta (S1) S1
(Note 3) (Note 3)
tdis (S1)
S2
(Note 3)
ta (S2) ta (OE) ten (OE) tdis (S2)
(Note 3)
OE
(Note 3)
tdis (OE) ten (S1) ten (S2)
(Note 3)
DQ1~8
W = "H" level
DATA VALID
Write cycle (W control mode)
tCW
A0~16
tsu (S1) S1
(Note 3) (Note 3)
S2
(Note 3)
tsu (S2)
(Note 3)
tsu (A-WH) OE
tsu (A) W
tw (W)
trec (W)
tdis (W) tdis (OE) DQ1~8 ten (W) DATA IN STABLE tsu (D) th (D)
ten(OE)
5
MITSUBISHI ELECTRIC
1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW A0~16
tsu (A)
tsu (S1)
trec (W)
S1
S2
(Note 3) (Note 5) (Note 3)
W
(Note 4) (Note 3) (Note 3)
tsu (D) DATA IN STABLE
th (D)
DQ1~8
Write cycle (S2 control mode)
tCW A0~16
S1
(Note 3) (Note 3)
tsu (A) S2
tsu (S2)
trec (W)
(Note 5)
W
(Note 3)
(Note 4) (Note 3)
tsu (D) DATA IN STABLE
th (D)
DQ1~8
Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while S2 high overlaps S1 and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode.
6
MITSUBISHI ELECTRIC
1997-4/1 MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L, -55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta = -40~85C, unless otherwise noted)
Symbol VCC (PD) VI (S1) VI (S2) Parameter Power down supply voltage Chip select input S1 Chip select input S2 2.2V Vcc(PD) 2V Vcc(PD) 2.2V 4.5V Vcc(PD) Vcc(PD) < 4.5V VCC = 3V -L 1) S2 0.2V, other inputs = 0~3V 2) S1 VCC - 0.2V,S2 VCC - 0.2V -LL other inputs = 0~3V Test conditions Min 2 2.2 Limits Typ Max Unit V
Vcc(PD)
V 0.8 0.2 100 V
ICC (PD)
Power down supply current
0.3
(Note 7)
20
A
Note7: ICC (PD) = 1A in case of Ta = 25C
(2) TIMING REQUIREMENTS (Ta = -40~85C, unless otherwise noted )
Symbol tsu (PD) trec (PD) Parameter Power down set up time Power down recovery time Test conditions Min 0 5 Limits Typ Max Unit ns ms
(3) POWER DOWN CHARACTERISTICS S1 control mode
VCC t su (PD) 4.5V 4.5V t rec (PD)
2.2V S1 S1 VCC - 0.2V
2.2V
S2 control mode
VCC 4.5V 4.5V t rec (PD)
S2
t su (PD)
0.2V S2 0.2V
0.2V
7
MITSUBISHI ELECTRIC

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